It is expected that future electronic systems will continue to require ever increasing speed and that they consume as little power as possible. To attain higher speeds and maintain low power consumption, integrated circuit (IC) chips, as one of the principle components of electronic systems, will need to operate at ever higher frequencies while consuming as little power as possible. For IC chips manufactured using CMOS technology, as device sizes shrink to increase speed and reduce chip size, increased static power consumption will become a major hurdle to attaining low power consumption goals. Static power is consumed by circuits, and, individual devices that are not actively changing states, i.e., the transistors are in a steady off state. Up until now, static power consumption in CMOS technology has been negligible. But the continued shrinking of device sizes will change this.
Continuing process advancements have allowed for reductions in critical dimensions in CMOS manufacturing. IC device dimensions have now reached or are about to reach a critical point where static power consumption will become a major concern unless new techniques are implemented to avoid unacceptable static power consumption levels. As device sizes have shrunk there has been a reduction in power supply voltage (Vdd). While lower Vdd corresponds to lower dynamic power consumption, it also reduces the speed of the device. To maintain or increase device speed, efforts have been pursued to reduce the threshold voltage (Vth) of transistors within a given process. However, the subthreshold voltage current, or leakage current, of a transistor exponentially increases with any Vth decrease. At prior larger device dimensions, this exponential leakage current increase was still negligible. But, at current and future device dimension sizes, this exponential increase in leakage current will result in a rapid and noticeable increase in static power consumption. Thus, without employing a new approach, the designer may be required to make unacceptable trade off decisions between speed and power consumption.
To counteract this increasing power consumption problem, it would be possible to increase the voltage threshold level of the transistors, however, this would have negative impacts on the transistor speed or frequency at which the device could be used. Furthermore, increasing Vth can introduce other problems because of noise margins that must be maintained within the device. It has been found that increasing Vth to more than Vdd/3 will negatively impact the functionality of the device.
As device sizes continue to shrink, this static power consumption issue will become more important for the entire semiconductor industry. This is particularly important now for makers of chips such as Field Programmable Devices (FPDs) with a large number of transistors on a single die, of which the majority will remain in a static off state.
An FPD is a programmable logic device comprised of an array of Configurable Logic Elements (CLEs) surrounded by a General Routing Matrix (GRM) with a periphery of input/output ports. In general, FPDs include programming elements such as static random access memory cells (SRAMs), antifuses, EPROMs, Flash cells, or EEPROMS. These memory elements are used to control the functions performed by the CLEs, the routing of signals in the GRM between CLEs, and the functionality of the input/output ports. Recently, FPD makers have trended toward providing a large number of drivers or buffers to support high fan out signals to be routed in the GRM. An FPD is designed to perform any logic function required by a user.
In practice, once a FPD user designs the function to be implemented by the FPD, and the FPD is programmed to perform the function, a large number of the resources available on the FPD are unused. Thus, the FPD may have a large percentage of transistors that are not being used at any given time. Xilinx, a leading manufacturer of FPDs, makes a variety of FPD known as a field programmable gate array (FPGA). Analysis of typical designs used by users of Xilinx FPGAs shows that anywhere from 60 to 90 percent of the FPGA resources are typically unused. These unused resources are in a static mode and thus as static power consumption increases for a given process the FPGA or FPD is likely to see large increases in overall power consumption.
It is desirable then to implement new circuit techniques that will operate at increased speeds and reduce leakage current in CMOS devices and thereby reduce IC chip power consumption.